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MC100LVEL38 3.3V ECL /2, /4/6 Clock Generation Chip
Description
The MC100LVEL38 is a low skew /2, /4/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended input signal. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. The Phase_Out output will go HIGH for one clock cycle whenever the /2 and the /4/6 outputs are both transitioning from a LOW to a HIGH. This output allows for clock synchronization within the system. Upon startup, the internal flip-flops will attain a random state; therefore, for systems which utilize multiple LVEL38s, the master reset (MR) input must be asserted to ensure synchronization. For systems which only use one LVEL38, the MR pin need not be exercised as the internal divider design ensures synchronization between the /2 and the /4/6 outputs of a single device. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.
Features
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SO-20 WB DW SUFFIX CASE 751D
MARKING DIAGRAM*
20 100LVEL38 AWLYYWWG
1 A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
*For additional marking information, refer to Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet.
* * * * * * * * *
50 ps Maximum Output-to-Output Skew Synchronous Enable/Disable Master Reset for Synchronization ESD Protection: >2 kV Human Body Model The 100 Series Contains Temperature Compensation PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.8 V Internal Input 75 kW Pulldown Resistors Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
* Moisture Sensitivity Level 1 * * *
For Additional Information, see Application Note AND8003/D Flammability Rating: UL 94 V-0 @ 0.125 in, Oxygen Index: 28 to 34 Transistor Count = 388 devices Pb-Free Packages are Available*
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
November, 2006 - Rev. 8
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Publication Order Number: MC100LVEL38/D
MC100LVEL38
VCC 20 Q0 19 Q0 18 Q1 17 Q1 16 Q2 15 Q2 14 Q3 13 Q3 12 VEE 11
1 VCC
2
3
4
5 CLK
6 VBB
7 MR
8
9
10
EN DIV_SEL CLK
VCC Phase_Out Phase_Out
Figure 1. Pinout: 20-Lead SOIC (Top View)
Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.
Q0 CLK CLK /2 R Q0 Q1 Q1 Q2 /4/6 R MR DIVSEL Phase Out R Logic VBB PHASE_OUT PHASE_OUT Q2 Q3 Q3
EN
R
Figure 2. Logic Diagram Table 1. PIN DESCRIPTION
Pin CLK, CLK Q0, Q1; Q0, Q1 Q2, Q3; Q2, Q3 EN MR DIVSEL Phase_Out, Phase_Out VBB VCC VEE Function ECL Diff Clock Inputs ECL Diff /2 Outputs ECL Diff /4/6 Outputs ECL Sync Enable Input ECL Master Reset Input ECL Frequency Select Input ECL Phase Sync Diff. Signal Output Reference Voltage Output Positive Supply Negative Supply
Table 2. FUNCTION TABLE
CLK Z ZZ X EN L H X MR L L H Function Divide Hold Q0-3 Reset Q0-3
Z = Low-to-High Transition ZZ = High-to-Low Transition X = Don't Care DVSEL L H Q2, Q3 OUTPUTS Divide by 4 Divide by 6
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MC100LVEL38
CLK Q (/2) Q (/4) Q (/6) Phase_Out (/4) Phase_Out (/6)
Figure 3. Timing Diagrams
Table 3. MAXIMUM RATINGS
Symbol VCC VEE VI Iout IBB TA Tstg qJA qJC Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Wave Solder Pb Pb-Free 0 lfpm 500 lfpm Standard Board <2 to 3 sec @ 248C <2 to 3 sec @ 260C SOIC-20 SOIC-20 SOIC-20 Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI VCC VI VEE Condition 2 Rating 8 to 0 -8 to 0 6 to 0 -6 to 0 50 100 0.5 -40 to +85 -65 to +150 90 60 30 to 35 265 265 Unit V V V V mA mA mA C C C/W C/W C/W C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
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MC100LVEL38
Table 4. LVPECL DC CHARACTERISTICS VCC = 3.3 V; VEE = 0.0 V (Note 1)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 2) Output LOW Voltage (Note 2) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 6) Input HIGH Current Input LOW Current 0.5 2215 1470 2135 1490 1.92 1.65 Min Typ 50 2295 1605 Max 60 2420 1745 2420 1825 2.04 2.75 150 0.5 2275 1490 2135 1490 1.92 1.65 Min 25C Typ 50 2345 1595 Max 60 2420 1680 2420 1825 2.04 2.75 150 0.5 2275 1490 2135 1490 1.92 1.65 Min 85C Typ 54 2345 1595 Max 65 2420 1680 2420 1825 2.04 2.75 150 Unit mA mV mV mV mV V V mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Input and output parameters vary 1:1 with VCC. VEE can vary 0.3 V. 2. Outputs are terminated through a 50 W resistor to VCC - 2.0 V. 3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPP Min and 1.0 V.
Table 5. LVNECL DC CHARACTERISTICS VCC = 0.0 V; VEE = -3.3 V (Note 4)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 5) Output LOW Voltage (Note 5) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 6) Input HIGH Current Input LOW Current 0.5 -1085 -1830 -1165 -1810 -1.38 -1.65 Min Typ 50 -1005 -1695 Max 60 -880 -1555 -880 -1475 -1.26 -0.55 150 0.5 -1025 -1810 -1165 -1810 -1.38 -1.65 Min 25C Typ 50 -955 -1705 Max 60 -880 -1620 -880 -1475 -1.26 -0.55 150 0.5 -1025 -1810 -1165 -1810 -1.38 -1.65 Min 85C Typ 54 -955 -1705 Max 65 -880 -1620 -880 -1475 -1.26 -0.55 150 Unit mA mV mV mV mV V V mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. Input and output parameters vary 1:1 with VCC. VEE can vary 0.3 V. 5. Outputs are terminated through a 50 W resistor to VCC - 2.0 V. 6. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPP Min and 1.0 V.
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MC100LVEL38
Table 6. AC CHARACTERISTICS VCC = 3.3 V; VEE = 0.0 V or VCC = 0.0 V; VEE = -3.3 V (Note 7)
-40C Symbol fmax tPLH tPHL Characteristic Maximum Toggle Frequency (Divide by 2) Propagation Delay to Output CLK to Q (Differential) CLK to Q (Single-Ended) CLK to Phase_Out (Differential) CLK to Phase_Out (Single-Ended) MR to.Q Within-Device Skew (Note 8) Part-to-Part tS tH VPP tRR tPW tr, tf Setup Time Hold Time Input Swing (Note 9) Reset Recovery Time Minimum Pulse Width CLK MR 800 700 280 550 Q0 - Q3 All Min 1.0 Typ 1.2 Max Min 1.0 25C Typ 1.2 Max Min 1.0 85C Typ 1.2 Max Unit GHz ps
810 710 800 750 510
1010 1010 1000 1050 810 50 75 200 240
850 750 840 790 540
1050 1050 1040 1090 840 50 75 200 240
900 800 890 840 570
1100 1100 1090 1140 870 50 75 200 240
tSKEW
ps
Q0 - Q3 (Differential) All EN to CLK DIVSEL to CLK CLK to EN CLK to Div_Sel CLK 150 150 200 250
150 150 200 1000 100 800 700 280 550 250 1000 100
150 150 200 250 1000 100 800 700 280 550
ps ps mV ps ps ps
Output Rise/Fall Times Q (20% - 80%)
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7. VEE can vary 0.3 V. 8. Skew is measured between outputs under identical transitions. 9. VPP(min) is minimum input swing for which AC parameters are guaranteed. The device will function reliably with differential inputs down to 100 mV.
Q Driver Device Q
Zo = 50 W
D Receiver Device
Zo = 50 W 50 W 50 W
D
VTT VTT = VCC - 2.0 V
Figure 4. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.)
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MC100LVEL38
ORDERING INFORMATION
Device MC100LVEL38DW MC100LVEL38DWG MC100LVEL38DWR2 MC100LVEL38DWR2G Package SOIC-20 SOIC-20 (Pb-Free) SOIC-20 SOIC-20 (Pb-Free) Package 38 Units / Rail 38 Units / Rail 1000 / Tape & Reel 1000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1672/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - ECLinPS I/O SPiCE Modeling Kit - Metastability and the ECLinPS Family - Interfacing Between LVDS and ECL - The ECL Translator Guide - Odd Number Counters Design - Marking and Date Codes - Termination of ECL Logic Devices - Interfacing with ECLinPS - AC Characteristics of ECL Devices
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MC100LVEL38
PACKAGE DIMENSIONS
SO-20 WB DW SUFFIX CASE 751D-05 ISSUE G
D
A
11 X 45 _
q
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
H
M
B
M
20
10X
0.25
E
1 10
20X
B 0.25
M
B TA
S
B
S
A e
SEATING PLANE
h
18X
A1
T
C
ECLinPS are registered trademarks of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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L
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MC100LVEL38/D

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